如何使用vsCode+Icarus verilog+GTKwave编写并仿真verilog 用VS Code + iverilog + GTKwave仿真Verilog【下载地址】用VSCodeiverilogGTKwave仿真Verilog分享用VS Code + iverilog + GTKwave仿真Verilog本资源文件提供了一个详细的教程，指导如何在VS Code中使用iverilog和GTKwave工具进行Verilog代码的仿真 项目地址: https://gitcode.com/Resource-Bundle-Collection/9dfab本资源文件提供了一个详细的教程，指导如何在VS Code中使用iverilog和GTKwave工具进行Verilog代码的仿真。通过本教程，您将学会如何配置VS Code环境，编写和编译Verilog代码，并使用GTKwave查看仿真波形。内容概述VS Code部分安装VS Code并配置Verilog插件。创建Verilog源代码文件并进行编辑。iverilog部分下载并安装iverilog编译器。使用iverilog编译Verilog代码生成VVP文件。GTKwave部分使用GTKwave查看仿真生成的VCD文件。调整波形显示以方便分析。使用步骤安装VS Code首先，下载并安装VS Code。安装完成后，打开VS Code并安装Verilog插件，以便在编辑Verilog代码时获得语法高亮和错误检查功能。编写Verilog代码在VS Code中创建一个新的Verilog文件，编写您的Verilog代码。您可以参考教程中的示例代码，编写一个简单的计数器模块。编写测试文件创建一个测试文件（testbench），用于测试您的Verilog模块。测试文件中应包含初始化代码、时钟生成代码以及仿真结束的控制代码。编译Verilog代码使用iverilog编译器将Verilog代码和测试文件编译成VVP文件。编译命令如下：iverilog -o "test_tb.vvp" test_tb.v test.v运行仿真在命令行中运行生成的VVP文件，生成VCD波形文件：vvp test_tb.vvp查看波形使用GTKwave打开生成的VCD文件，查看仿真波形。您可以通过调整波形显示来分析仿真结果。注意事项确保iverilog和GTKwave已正确安装并配置好环境变量。在编写Verilog代码时，注意模块的输入输出定义和时序逻辑的正确性。在仿真过程中，可以通过调整测试文件中的参数来验证不同条件下的仿真结果。通过本教程，您将能够熟练使用VS Code、iverilog和GTKwave进行Verilog代码的仿真，为硬件设计提供强大的支持。【下载地址】用VSCodeiverilogGTKwave仿真Verilog分享用VS Code + iverilog + GTKwave仿真Verilog本资源文件提供了一个详细的教程，指导如何在VS Code中使用iverilog和GTKwave工具进行Verilog代码的仿真 项目地址: https://gitcode.com/Resource-Bundle-Collection/9dfab————————————————版权声明：本文为CSDN博主「邱蒙励」的原创文章，遵循CC 4.0 BY-SA版权协议，转载请附上原文出处链接及本声明。原文链接：https://blog.csdn.net/gitblog_06576/article/details/143385319

Vscode自动生成verilog例化 前言veirlog模块例化的时候，辣么多的信号端子，手动例化又慢又容易出错，葵花妈妈开课啦，孩子手残老犯错怎么办？当然是脚本一劳永逸，妈妈再也不担心手残党。流程（1）在vscode中安装如下插件。（2）在电脑中安装python3以上的环境。下载地址：https://www.python.org/downloads/release/python-373/安装记得一定要勾选添加路径，记得管理员安装。重启你的电脑。在cmd窗口输入python即可验证是否安装成功！（3）安装chardet。为确保插件可用，这个需要安装。参考链接：https://blog.csdn.net/sinat_28631741/article/details/80483064方式一 源码按照：第一步：下载压缩文件，例如： 'chardet-3.0.4.tar.gz'； 第二步：解压文件到python安装位置下的‘site-packages’目录下，例如：‘D:\python2.7\Lib\site-packages’； 第三步：打开终端命令窗口，进入解压的‘chardet’目录下，执行命令：python setup.py install （4）修改插件的原始py文件，觉得开发者的py有瑕疵，让帅气的同事重新整了个，把以下代码替换进原始py文件即可。在打开v文件的vscode下按ctrl+p，输入instance可出现下述界面。替换此py文件的代码即可。 #! /usr/bin/env python ''' vTbgenerator.py -- generate verilog module Testbench generated bench file like this: fifo_sc #( .DATA_WIDTH ( 8 ), .ADDR_WIDTH ( 8 ) ) u_fifo_sc ( .CLK ( CLK ), .RST_N ( RST_N ), .RD_EN ( RD_EN ), .WR_EN ( WR_EN ), .DIN ( DIN [DATA_WIDTH-1 :0] ), .DOUT ( DOUT [DATA_WIDTH-1 :0] ), .EMPTY ( EMPTY ), .FULL ( FULL ) ); Usage: python vTbgenerator.py ModuleFileName.v ''' import random import re import sys from queue import Queue import chardet def delComment(Text): """ removed comment """ single_line_comment = re.compile(r"//(.*)$", re.MULTILINE) multi_line_comment = re.compile(r"/\*(.*?)\*/", re.DOTALL) Text = multi_line_comment.sub('\n', Text) Text = single_line_comment.sub('\n', Text) return Text def delBlock(Text): """ removed task and function block """ Text = re.sub(r'\Wtask\W[\W\w]*?\Wendtask\W', '\n', Text) Text = re.sub(r'\Wfunction\W[\W\w]*?\Wendfunction\W', '\n', Text) return Text def findName(inText): """ find module name and port list""" p = re.search(r'([a-zA-Z_][a-zA-Z_0-9]*)\s*', inText) mo_Name = p.group(0).strip() return mo_Name def paraDeclare(inText, portArr): """ find parameter declare """ pat = r'\s' + portArr + r'\s[\w\W]*?[;,)]' ParaList = re.findall(pat, inText) return ParaList def portDeclare(inText, portArr): """find port declare, Syntax: input [ net_type ] [ signed ] [ range ] list_of_port_identifiers return list as : (port, [range]) """ port_definition = re.compile( r'\b' + portArr + r''' (\s+(wire|reg)\s+)* (\s*signed\s+)* (\s*\[.*?:.*?\]\s*)* (?P<port_list>.*?) (?= \binput\b | \boutput\b | \binout\b | ; | \) ) ''', re.VERBOSE | re.MULTILINE | re.DOTALL ) pList = port_definition.findall(inText) t = [] for ls in pList: if len(ls) >= 2: t = t + portDic(ls[-2:]) return t def portDic(port): """delet as : input a =c &d; return list as : (port, [range]) """ pRe = re.compile(r'(.*?)\s*=.*', re.DOTALL) pRange = port[0] pList = port[1].split(',') pList = [i.strip() for i in pList if i.strip() != ''] pList = [(pRe.sub(r'\1', p), pRange.strip()) for p in pList] return pList def formatPort(AllPortList, isPortRange=1): PortList = AllPortList str = '' if PortList != []: l1 = max([len(i[0]) for i in PortList])+2 l3 = max(18, l1) strList = [] str = ',\n'.join([' ' * 4 + '.' + i[0].ljust(l3) + '(' + (i[0]) + ')' for i in AllPortList]) strList = strList + [str] str = ',\n\n'.join(strList) return str def formatDeclare(PortList, portArr, initial=""): str = '' if PortList != []: str = '\n'.join([portArr.ljust(4) + ' '+(i[1]+min(len(i[1]), 1)*' ' + i[0]) + ';' for i in PortList]) return str def formatPara(ParaList): paraDec = '' paraDef = '' if ParaList != []: s = '\n'.join(ParaList) pat = r'([a-zA-Z_][a-zA-Z_0-9]*)\s*=\s*([\w\W]*?)\s*[;,)]' p = re.findall(pat, s) l1 = max([len(i[0]) for i in p]) l2 = max([len(i[1]) for i in p]) paraDec = '\n'.join(['parameter %s = %s;' % (i[0].ljust(l1 + 1), i[1].ljust(l2)) for i in p]) paraDef = '#(\n' + ',\n'.join([' .' + i[0].ljust(l1 + 1) + '( ' + i[1].ljust(l2)+' )' for i in p]) + ')\n' return paraDec, paraDef def portT(inText, ioPadAttr): x = {} count_list = [] order_list = [] for i in ioPadAttr: p = port_index_list(inText, i) for j in p: count_list.append(j) x[j] = i count_list = quick_sort(count_list, 0, len(count_list)-1) for c in count_list: order_list.append(x.get(c)) return order_list def quick_sort(myList, start, end): if start < end: i, j = start, end base = myList[i] while i < j: while (i < j) and (myList[j] >= base): j = j - 1 myList[i] = myList[j] while (i < j) and (myList[i] <= base): i = i + 1 myList[j] = myList[i] myList[i] = base quick_sort(myList, start, i - 1) quick_sort(myList, j + 1, end) return myList def formatPort_order(padAttr, orderList): for p in padAttr: q = Queue() for i in padAttr.get(p): q.put(i) padAttr[p] = q AllPortList = [] for o in orderList: AllPortList.append(padAttr.get(o).get()) return AllPortList def port_index_list(intext, text): l = [] t = intext index = t.find(text) while index > -1: t = t.replace(text, random_str(len(text)), 1) l.append(index) index = t.find(text) return l def random_str(size): s = '' for i in range(size): s += str(random.randint(0, 9)) return s def getPortMap(AllPortList, ioPadAttr): if len(AllPortList) != len(ioPadAttr): return p_map = {} for i in range(len(AllPortList)): p_map[ioPadAttr[i]] = AllPortList[i] return p_map def writeTestBench(input_file): """ write testbench to file """ with open(input_file, 'rb') as f: f_info = chardet.detect(f.read()) f_encoding = f_info['encoding'] with open(input_file, encoding=f_encoding) as inFile: inText = inFile.read() # removed comment,task,function inText = delComment(inText) inText = delBlock(inText) # moduel ... endmodule # moPos_begin = re.search(r'(\b|^)module\b', inText).end() moPos_end = re.search(r'\bendmodule\b', inText).start() inText = inText[moPos_begin:moPos_end] name = findName(inText) paraList = paraDeclare(inText, 'parameter') paraDec, paraDef = formatPara(paraList) ioPadAttr = ['input', 'output', 'inout'] orlder = portT(inText, ioPadAttr) input = portDeclare(inText, ioPadAttr[0]) output = portDeclare(inText, ioPadAttr[1]) inout = portDeclare(inText, ioPadAttr[2]) portList = formatPort(formatPort_order( getPortMap([input, output, inout], ioPadAttr), orlder)) input = formatDeclare(input, 'reg') output = formatDeclare(output, 'wire') inout = formatDeclare(inout, 'wire') # write Instance # module_parameter_port_list if(paraDec != ''): print("// %s Parameters\n%s\n" % (name, paraDec)) # list_of_port_declarations #print("// %s Inputs\n%s\n" % (name, input)) #print("// %s Outputs\n%s\n" % (name, output)) #if(inout != ''): # print("// %s Bidirs\n%s\n" % (name, inout)) print("\n") # UUT print("%s %s inst_%s (\n%s\n);" % (name, paraDef, name, portList)) if __name__ == '__main__': writeTestBench(sys.argv[1]) （5）享受一下吧。比如我们有如下代码：crtl+p，输入instance，按回车即可。 复制粘贴大发好。以上。转载于:https://www.cnblogs.com/kingstacker/p/9944259.html

uvmgen的使用及其产生的UVM环境介绍 前言UVM是IC验证的一种方法学，利用UVM搭建的验证环境基本框架都类似，因此，可以通过脚本来生成UVM的验证环境基本框架。本文主要介绍synopsys公司，在vcs工具中自带的一个脚本uvmgen，通过这个脚本，可以自动产生一整套UVM的验证环境，或者也可以只生成其中的一个UVM组件。一、uvmgen的使用首先利用uvmgen这个脚本，产生一个完整的UVM环境；然后运行这个环境，解决一些系统、工具、UVM环境之间的一些兼容性问题。1.1 uvmgen产生一个完整UVM环境这里展示一下，如何通过uvmgen这个脚本，产生一个完整的UVM环境。 hefei@ubuntu:~$ which uvmgen /opt/synopsys/vcs_vO-2018.09-SP2/bin/uvmgen hefei@ubuntu:~$ uvmgen ------------------------------------------------------------ WELCOME TO UVM TEMPLATE GENERATOR ------------------------------------------------------------ UVM templates compatible to UVM 1.1/1.2 used. Using template from /opt/synopsys/vcs_vO-2018.09-SP2/etc/uvm_template/shared/lib/templates/uvm 1) Enter 1 to Create Complete Environment 2) Enter 2 to Generate Individual Template Select [1-2]: 1 Do you want to create your own methods [Instead of UVM shorthand macros] ? Select [ y/Y/n/N ][Default: n]: n Would you be associating UVM REG models in your environment class? enter (y/n) [Default: n]:y Enter Name of RAL Adapter:ral_ad1 Enter the environment name: top_env Do you want to create Agents? Select(y/Y/n/N) [Default: n]:y Enter Master agent data Enter name of master agent: mst Enter name of sequencer: sqr1 Enter name of driver: drv1 Enter name of monitor: mon1 Enter name of interface: intf1 Enter name of the transaction: tr1 Is this transaction class extended from a BU class? enter (y/n): n Enter Slave agent data Enter name of slave agent: slv Enter name of sequencer: sqr2 Enter name of driver: drv2 Enter name of monitor: mon2 Enter name of interface: intf2 Do you want to use same transaction class for master and slave agents ? enter (y/n):y Choose one of the following ral bfm: 1) RAL sequence adapter, single domain 2) RAL sequence adapter, multiplexed domains select [1-2]:2 Enter Name of second RAL Adapter:ral_ad2 Enter Driver information for the slave agent slv :: Choose one of following driver available 1) Driver, PUSH DRIVER (uvm_push_driver) 2) Driver, PULL DRIVER (uvm_driver) Select [1- 2] [Default: 2]: Enter Driver information for the master agent mst :: Choose one of following driver available 1) Driver, PUSH DRIVER (uvm_push_driver) 2) Driver, PULL DRIVER (uvm_driver) Select [1- 2] [Default: 2]: Would you like to implement scoreboard? Select(y/Y/n/N) [Default: y]:y Enter Name of Scoreboard Class:scb The testcase generated is top_env_test ------------------------------------------------------------ Template generation completed. ------------------------------------------------------------ Usage notes : 1) Find the generated files in "proj/top_env" directory. 2) Makefile has been placed in run "proj/top_env/run" directory. 3) Edit files and look for comments marked "ToDo:" and fill in the application-specific behavior for your function. ------------------------------------------------------------ 执行完成上面的脚本后，在执行的目录下，会产生一个proj的文件夹，该文件夹的层次结构如下所示： hefei@ubuntu:~/proj$ tree . ├── README ├── top_env │ ├── doc │ ├── env │ │ ├── mst.sv │ │ ├── slv.sv │ │ ├── top_env_ral_env.sv │ │ └── top_env.ralf │ ├── examples │ ├── hdl │ │ └── top_env_top.sv │ ├── include │ │ ├── mstr_slv_intfs.incl │ │ ├── mstr_slv_src.incl │ │ └── top_env.sv │ ├── run │ │ └── Makefile │ ├── src │ │ ├── mon_2cov.sv │ │ ├── mst_drv1.sv │ │ ├── mst_intf1.sv │ │ ├── mst_mon1.sv │ │ ├── mst_sequence_library.sv │ │ ├── mst_sqr1.sv │ │ ├── mst_tr1.sv │ │ ├── ral_multiplexed.sv │ │ ├── scb.sv │ │ ├── slv_drv2.sv │ │ ├── slv_intf2.sv │ │ ├── slv_mon2.sv │ │ ├── slv_sqr2.sv │ │ ├── slv_tr1.sv │ │ ├── top_env_cfg.sv │ │ └── top_env_cov.sv │ └── tests │ ├── top_env_tb_mod.sv │ └── top_env_test.sv └── uvmgen_options_log.txt 1.2 解决运行报错的问题直接进入到proj/top_env/run这个文件夹，执行make后，会报如下错误，这是因为我们的系统是64位的，而执行ralgen和vcs的时候都没有加上-full64这个选项。 hefei@ubuntu:~/proj/top_env/run$ make rm -rf simv* csrc rm -rf vc_hdrs.h .vcsmx_rebuild *.log rm -rf work/* *.svshell vcs_version cd ../env; ralgen -uvm -l sv -t top_env -c b -c a -c f top_env.ralf;cd - Error: Bad VMM installation. Executable 'ralgen.binary' not visible. /home/hefei/proj/top_env/run vcs -sverilog -l vcs.log -debug_pp +incdir+/opt/uvm-1.2/src /opt/uvm-1.2/src/uvm_pkg.sv /opt/uvm-1.2/src/dpi/uvm_dpi.cc -CFLAGS -DVCS +incdir+../include+../src+../env+../tests+../hdl \ ../tests/top_env_tb_mod.sv ../hdl/top_env_top.sv Error-[VCS_COM_UNE] Cannot find VCS compiler VCS compiler not found. Environment variable VCS_HOME (/opt/synopsys/vcs_vO-2018.09-SP2/linux) is selecting a directory in which there isn't a compiler '/opt/synopsys/vcs_vO-2018.09-SP2/linux/bin/vcs1' for a machine of this type 'linux'. Please check whether 'VCS_HOME' is incorrect; if not, see below. Perhaps vcs hasn't been installed for machine of type "linux". Or the installation has been damaged. To verify whether vcsO-2018.09 supports machine of type "Linux 5.4.0-77-generic", please look at ReleaseNotes for more details . We determine the machine type from uname; maybe uname is incorrect. You can fix installation problems by reinstalling from CDROM or downloading it from the Synopsys ftp server. For assistance, please contact vcs technical support at vcs_support@synopsys.com or call 1-800-VERILOG Makefile:61: recipe for target 'comp' failed make: *** [comp] Error 1 打开Makefile文件，在41行COMP_OPTS，以及61行ralgen后面，分别加入-full64选项，如下代码所示。 COMP_OPTS = -full64 -sverilog -l vcs.log $(UVM) $(INCL) $(DEFINES) cd ../env; ralgen -full64 -uvm -l sv -t top_env -c b -c a -c f top_env.ralf;cd - 重新make后，遇到的libvcsnew.so: undefined reference to问题，可以参考如下链接进行解决。libvcsnew.so: undefined reference to加入-LDFLAGS -Wl,–no-as-needed选项后，代码如下： COMP_OPTS = -full64 -sverilog -LDFLAGS -Wl,--no-as-needed -l vcs.log $(UVM) $(INCL) $(DEFINES) 一键获取完整项目代码再重新make后，得到的仿真log如下所示 ./simv -l simv.log \ +ntb_random_seed=1 +UVM_TESTNAME=top_env_test Chronologic VCS simulator copyright 1991-2018 Contains Synopsys proprietary information. Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Jun 24 19:47 2021 UVM_INFO /opt/uvm-1.2/src/base/uvm_root.svh(392) @ 0: reporter [UVM/RELNOTES] ---------------------------------------------------------------- UVM-1.2 (C) 2007-2014 Mentor Graphics Corporation (C) 2007-2014 Cadence Design Systems, Inc. (C) 2006-2014 Synopsys, Inc. (C) 2011-2013 Cypress Semiconductor Corp. (C) 2013-2014 NVIDIA Corporation ---------------------------------------------------------------- *********** IMPORTANT RELEASE NOTES ************ You are using a version of the UVM library that has been compiled with `UVM_NO_DEPRECATED undefined. See http://www.eda.org/svdb/view.php?id=3313 for more details. You are using a version of the UVM library that has been compiled with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined. See http://www.eda.org/svdb/view.php?id=3770 for more details. (Specify +UVM_NO_RELNOTES to turn off this notice) UVM_INFO @ 0: reporter [RNTST] Running test top_env_test... UVM_INFO /opt/uvm-1.2/src/base/uvm_spell_chkr.svh(123) @ 0: reporter [UVM/CONFIGDB/SPELLCHK] include_coverage not located, did you mean default_sequence Note-[FCICIO] Instance coverage is ON /home/hefei/proj/top_env/run/../env/ral_top_env.sv, 161 top_env_tb_mod, "top_env_tb_mod::ral_block_top_env::cg_addr" Instance coverage is set (option.per_instance = 1) for covergroup 'top_env_tb_mod::ral_block_top_env::cg_addr' Covergroup Instance: me.obj.cg_addr Design hierarchy: top_env_top.test UVM_INFO /opt/uvm-1.2/src/base/uvm_spell_chkr.svh(123) @ 0: reporter [UVM/CONFIGDB/SPELLCHK] include_coverage not located, did you mean default_sequence Note-[FCICIO] Instance coverage is ON /home/hefei/proj/top_env/run/../env/ral_top_env.sv, 14 top_env_tb_mod, "top_env_tb_mod::ral_reg_top_env_CHIP_ID::cg_bits" Instance coverage is set (option.per_instance = 1) for covergroup 'top_env_tb_mod::ral_reg_top_env_CHIP_ID::cg_bits' Covergroup Instance: me.obj.cg_bits Design hierarchy: top_env_top.test UVM_INFO /opt/uvm-1.2/src/base/uvm_spell_chkr.svh(123) @ 0: reporter [UVM/CONFIGDB/SPELLCHK] include_coverage not located, did you mean default_sequence UVM_INFO /opt/uvm-1.2/src/base/uvm_root.svh(579) @ 0: reporter [UVMTOP] UVM testbench topology: -------------------------------------------------------------------------- Name Type Size Value -------------------------------------------------------------------------- uvm_test_top top_env_test - @423 env top_env_ral_env - @436 cov top_env_cov - @467 Coverage Analysis uvm_analysis_imp - @476 master_agent mst - @449 mast_drv drv1 - @688 rsp_port uvm_analysis_port - @707 seq_item_port uvm_seq_item_pull_port - @697 mast_mon mon1 - @532 mon_analysis_port uvm_analysis_port - @541 mast_sqr sqr1 - @551 rsp_export uvm_analysis_export - @560 seq_item_export uvm_seq_item_pull_imp - @678 arbitration_queue array 0 - lock_queue array 0 - num_last_reqs integral 32 'd1 num_last_rsps integral 32 'd1 mon2cov mon1_2cov_connect - @486 sb scb - @495 after_export uvm_analysis_export - @736 before_export uvm_analysis_export - @726 comparator uvm_in_order_class_comparator #(T) - @746 after uvm_tlm_analysis_fifo #(T) - @844 analysis_export uvm_analysis_imp - @893 get_ap uvm_analysis_port - @883 get_peek_export uvm_get_peek_imp - @863 put_ap uvm_analysis_port - @873 put_export uvm_put_imp - @853 after_export uvm_analysis_export - @765 before uvm_tlm_analysis_fifo #(T) - @785 analysis_export uvm_analysis_imp - @834 get_ap uvm_analysis_port - @824 get_peek_export uvm_get_peek_imp - @804 put_ap uvm_analysis_port - @814 put_export uvm_put_imp - @794 before_export uvm_analysis_export - @755 pair_ap uvm_analysis_port - @775 slave_agent slv - @458 drv drv2 - @923 rsp_port uvm_analysis_port - @942 seq_item_port uvm_seq_item_pull_port - @932 mon mon2 - @904 mon_analysis_port uvm_analysis_port - @913 slv_seqr sqr2 - @952 rsp_export uvm_analysis_export - @961 seq_item_export uvm_seq_item_pull_imp - @1079 arbitration_queue array 0 - lock_queue array 0 - num_last_reqs integral 32 'd1 num_last_rsps integral 32 'd1 -------------------------------------------------------------------------- UVM_INFO /opt/uvm-1.2/src/base/uvm_factory.svh(1645) @ 0: reporter [UVM/FACTORY/PRINT] #### Factory Configuration (*) No instance or type overrides are registered with this factory All types registered with the factory: 80 total Type Name --------- REGTR base_sequence drv1 drv2 mon1 mon1_2cov_connect mon2 mst ral_ad2 ral_block_top_env ral_mem_top_env_top_env_RAM ral_reg_top_env_CHIP_ID reg_seq scb sequence_0 sequence_1 slv sqr1 sqr1_sequence_library sqr2 top_env_cfg top_env_cov top_env_ral_env top_env_test tr1 (*) Types with no associated type name will be printed as <unknown> #### UVM_INFO ../src/mst_drv1.sv(121) @ 0: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_mon1.sv(133) @ 0: uvm_test_top.env.master_agent.mast_mon [top_env_MONITOR] Starting transaction... UVM_INFO ../src/mst_mon1.sv(137) @ 0: uvm_test_top.env.master_agent.mast_mon [top_env_MONITOR] User need to add monitoring logic $finish called from file "../src/mst_mon1.sv", line 138. $finish at simulation time 0 V C S S i m u l a t i o n R e p o r t Time: 0 CPU Time: 1.110 seconds; Data structure size: 0.4Mb 到此为止，通过uvmgen脚本生成的整个UVM环境已经能够正常运行。uvmgen还可以生成单个的UVM组件，以及快速产生一个完整的UVM环境的方法，更多关于uvmgen脚本的使用方法，可以参考如下文档。uvmgen_userguide.pdf二、uvmgen产生的UVM环境拿到这个环境，首先，了解一下这个环境的框架，其次想着打印一下接口的波形，看看时钟复位是否正确；最后，要解决仿真异常结束的问题，上面仿真执行的log显示，$finish called from file “…/src/mst_mon1.sv”, line 138.，这不是UVM仿真的正常结束的log。2.1 环境框架uvmgen产生的uvm环境的框架如下图所示：2.2 添加打印波形打开顶层文件proj/top_env/hdl/top_env_top.sv，加入如下代码实现打印波形。 initial $fsdbDumpvars(); 重新make后，遇到的Undefined System Task call to '$fsdbDumpfile '问题，解决方法参考如下：Undefined System Task call to ‘$fsdbDumpfile’之后打开fsdb波形，调出时钟和复位信号后，显示正常，并没有像下文所述存在bug的情况，虽然VCS版本不同，但对比了时钟复位产生的源代码都是一致的。2011版VCS自带的工具UVMGEN的一个BUG，很难想像有这种级别的BUG～～2.3 解决仿真异常结束的问题仿真执行的log显示，$finish called from file “…/src/mst_mon1.sv”, line 138.，这不是UVM仿真的正常结束的log，对应的sequence激励也没有下发。打开proj/top_env/src/mst_mon1.sv，定位到138行，将138行的finish屏蔽，在130行加入一个wait(0)，避免mon1中的forever循环一直刷log(这里只是临时处理一下，后期填入代码的时候需要将其去掉)，如下图所示。同样的方式处理proj/top_env/src/slv_mon2.sv文件。再重新make，通过下面的log，可以看到仿真已经正常结束，sequence中的激励，也已经下发到了drver中。 ./simv -l simv.log \ +ntb_random_seed=1 +UVM_TESTNAME=top_env_test Chronologic VCS simulator copyright 1991-2018 Contains Synopsys proprietary information. Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Jun 25 00:02 2021 UVM_INFO /opt/uvm-1.2/src/base/uvm_root.svh(392) @ 0: reporter [UVM/RELNOTES] ---------------------------------------------------------------- UVM-1.2 (C) 2007-2014 Mentor Graphics Corporation (C) 2007-2014 Cadence Design Systems, Inc. (C) 2006-2014 Synopsys, Inc. (C) 2011-2013 Cypress Semiconductor Corp. (C) 2013-2014 NVIDIA Corporation ---------------------------------------------------------------- *********** IMPORTANT RELEASE NOTES ************ You are using a version of the UVM library that has been compiled with `UVM_NO_DEPRECATED undefined. See http://www.eda.org/svdb/view.php?id=3313 for more details. You are using a version of the UVM library that has been compiled with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined. See http://www.eda.org/svdb/view.php?id=3770 for more details. (Specify +UVM_NO_RELNOTES to turn off this notice) UVM_INFO @ 0: reporter [RNTST] Running test top_env_test... *Verdi* Loading libsscore_vcs201809.so FSDB Dumper for VCS, Release Verdi_O-2018.09-SP2, Linux x86_64/64bit, 02/21/2019 (C) 1996 - 2019 by Synopsys, Inc. *Verdi* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file. *Verdi* : Create FSDB file 'novas.fsdb' *Verdi* : Begin traversing the scopes, layer (0). *Verdi* : End of traversing. UVM_INFO /opt/uvm-1.2/src/base/uvm_spell_chkr.svh(123) @ 0: reporter [UVM/CONFIGDB/SPELLCHK] include_coverage not located, did you mean default_sequence Note-[FCICIO] Instance coverage is ON /home/hefei/proj/top_env/run/../env/ral_top_env.sv, 161 top_env_tb_mod, "top_env_tb_mod::ral_block_top_env::cg_addr" Instance coverage is set (option.per_instance = 1) for covergroup 'top_env_tb_mod::ral_block_top_env::cg_addr' Covergroup Instance: me.obj.cg_addr Design hierarchy: top_env_top.test UVM_INFO /opt/uvm-1.2/src/base/uvm_spell_chkr.svh(123) @ 0: reporter [UVM/CONFIGDB/SPELLCHK] include_coverage not located, did you mean default_sequence Note-[FCICIO] Instance coverage is ON /home/hefei/proj/top_env/run/../env/ral_top_env.sv, 14 top_env_tb_mod, "top_env_tb_mod::ral_reg_top_env_CHIP_ID::cg_bits" Instance coverage is set (option.per_instance = 1) for covergroup 'top_env_tb_mod::ral_reg_top_env_CHIP_ID::cg_bits' Covergroup Instance: me.obj.cg_bits Design hierarchy: top_env_top.test UVM_INFO /opt/uvm-1.2/src/base/uvm_spell_chkr.svh(123) @ 0: reporter [UVM/CONFIGDB/SPELLCHK] include_coverage not located, did you mean default_sequence UVM_INFO /opt/uvm-1.2/src/base/uvm_root.svh(579) @ 0: reporter [UVMTOP] UVM testbench topology: -------------------------------------------------------------------------- Name Type Size Value -------------------------------------------------------------------------- uvm_test_top top_env_test - @423 env top_env_ral_env - @436 cov top_env_cov - @467 Coverage Analysis uvm_analysis_imp - @476 master_agent mst - @449 mast_drv drv1 - @688 rsp_port uvm_analysis_port - @707 seq_item_port uvm_seq_item_pull_port - @697 mast_mon mon1 - @532 mon_analysis_port uvm_analysis_port - @541 mast_sqr sqr1 - @551 rsp_export uvm_analysis_export - @560 seq_item_export uvm_seq_item_pull_imp - @678 arbitration_queue array 0 - lock_queue array 0 - num_last_reqs integral 32 'd1 num_last_rsps integral 32 'd1 mon2cov mon1_2cov_connect - @486 sb scb - @495 after_export uvm_analysis_export - @736 before_export uvm_analysis_export - @726 comparator uvm_in_order_class_comparator #(T) - @746 after uvm_tlm_analysis_fifo #(T) - @844 analysis_export uvm_analysis_imp - @893 get_ap uvm_analysis_port - @883 get_peek_export uvm_get_peek_imp - @863 put_ap uvm_analysis_port - @873 put_export uvm_put_imp - @853 after_export uvm_analysis_export - @765 before uvm_tlm_analysis_fifo #(T) - @785 analysis_export uvm_analysis_imp - @834 get_ap uvm_analysis_port - @824 get_peek_export uvm_get_peek_imp - @804 put_ap uvm_analysis_port - @814 put_export uvm_put_imp - @794 before_export uvm_analysis_export - @755 pair_ap uvm_analysis_port - @775 slave_agent slv - @458 drv drv2 - @923 rsp_port uvm_analysis_port - @942 seq_item_port uvm_seq_item_pull_port - @932 mon mon2 - @904 mon_analysis_port uvm_analysis_port - @913 slv_seqr sqr2 - @952 rsp_export uvm_analysis_export - @961 seq_item_export uvm_seq_item_pull_imp - @1079 arbitration_queue array 0 - lock_queue array 0 - num_last_reqs integral 32 'd1 num_last_rsps integral 32 'd1 -------------------------------------------------------------------------- UVM_INFO /opt/uvm-1.2/src/base/uvm_factory.svh(1645) @ 0: reporter [UVM/FACTORY/PRINT] #### Factory Configuration (*) No instance or type overrides are registered with this factory All types registered with the factory: 80 total Type Name --------- REGTR base_sequence drv1 drv2 mon1 mon1_2cov_connect mon2 mst ral_ad2 ral_block_top_env ral_mem_top_env_top_env_RAM ral_reg_top_env_CHIP_ID reg_seq scb sequence_0 sequence_1 slv sqr1 sqr1_sequence_library sqr2 top_env_cfg top_env_cov top_env_ral_env top_env_test tr1 (*) Types with no associated type name will be printed as <unknown> #### UVM_INFO ../src/mst_drv1.sv(121) @ 0: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/slv_drv2.sv(121) @ 0: uvm_test_top.env.slave_agent.drv [top_env_DRIVER] Starting transaction... UVM_INFO /opt/uvm-1.2/src/seq/uvm_sequence_library.svh(659) @ 0: uvm_test_top.env.master_agent.mast_sqr@@sqr1_sequence_library [SEQLIB/START] Starting sequence library sqr1_sequence_library in main phase: 10 iterations in mode UVM_SEQ_LIB_RAND UVM_INFO ../src/mst_drv1.sv(137) @ 0: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 0: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 100: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 100: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 200: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 200: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 300: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 300: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 400: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 400: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 500: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 500: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 600: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 600: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 700: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 700: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 800: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 800: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 900: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 900: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 1000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 1000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 1100: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 1100: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 1200: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 1200: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 1300: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 1300: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 1400: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 1400: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 1500: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 1500: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 1600: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 1600: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 1700: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 1700: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 1800: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 1800: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 1900: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 1900: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2100: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2100: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2200: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2200: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2300: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2300: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2400: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2400: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2500: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2500: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2600: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2600: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2700: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2700: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2800: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2800: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 2900: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 2900: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO ../src/mst_drv1.sv(137) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Completed transaction... UVM_INFO ../src/mst_drv1.sv(121) @ 3000: uvm_test_top.env.master_agent.mast_drv [top_env_DRIVER] Starting transaction... UVM_INFO /opt/uvm-1.2/src/seq/uvm_sequence_library.svh(736) @ 3000: uvm_test_top.env.master_agent.mast_sqr@@sqr1_sequence_library [SEQLIB/END] Ending sequence library in phase main UVM_INFO ../src/scb.sv(50) @ 3000: uvm_test_top.env.sb [SBRPT] Matches = 0, Mismatches = 0 UVM_INFO /opt/uvm-1.2/src/base/uvm_report_server.svh(847) @ 3000: reporter [UVM/REPORT/SERVER] --- UVM Report Summary --- ** Report counts by severity UVM_INFO : 212 UVM_WARNING : 0 UVM_ERROR : 0 UVM_FATAL : 0 ** Report counts by id [RNTST] 1 [SBRPT] 1 [SEQLIB/END] 1 [SEQLIB/START] 1 [UVM/CONFIGDB/SPELLCHK] 3 [UVM/FACTORY/PRINT] 1 [UVM/RELNOTES] 1 [UVMTOP] 1 [top_env_DRIVER] 202 $finish called from file "/opt/uvm-1.2/src/base/uvm_root.svh", line 517. $finish at simulation time 3000 V C S S i m u l a t i o n R e p o r t Time: 3000 CPU Time: 1.350 seconds; Data structure size: 0.5Mb到此为止，通过uvmgen脚本产生的UVM环境框架，已经正常编译仿真，下面需要做的就是，根据我们自己的项目，往对应的组件里边填入具体的实现，需要修改的组件包括driver、monitor、sequence、regmodel、coverage等。2.3 发现环境中存在的一些问题问题一：monitor组件获取不到interface。不管是mst还是slv中的monitor组件，一方面是get的时候用的标签，和前面set的不一致，导致get不到interface；另一方面，没有去判断get到的句柄是否为空。修改mst_mon1的代码如下所示：主要修改的地方有两点：1、85行get函数的第三个参数标签由mon_if改为mst_if；2、添加91和92行，用于检测mst_mon1中是否get到interface，如果get不到，立马结束仿真。slv_mon2的代码修改方式和mst_mon1类似，标签改成slv_if。至于与这些get任务相对应的set任务在哪里，可以参考如下帖子：如何定位uvm_config_db get任务的来源总的来说，agt、drv、mon中的get任务都来自proj/top_env/tests/top_env_tb_mod.sv中，19和20行的两个set任务，当set任务前面两个参数为空的情况下，应该是全域去set，因此可以在uvm所有地方都能get到这个interface。最后，需要将proj/top_env/env/mst.sv和proj/top_env/env/slv.sv的38和39行注释掉，如下图所示，这是因为，这个set函数将自己的interface传递给自己没有任何意义，而且在仿真的时候，通过 +UVM_CONFIG_DB_TRACE加入这个宏之后，还会debug报错。总结本文首先记录了利用uvmgen这个脚本，去产生一个完整的UVM验证环境框架的方法；然后解决了一些系统、工具、UVM环境之间的兼容性问题；最后发现并解决了，脚本生成的UVM验证环境框架中，在通过config_db传递interface时候的问题。————————————————版权声明：本文为CSDN博主「hh199203」的原创文章，遵循CC 4.0 BY-SA版权协议，转载请附上原文出处链接及本声明。原文链接：https://blog.csdn.net/hh199203/article/details/118210541

后仿中$setup,$hold与$setuphold 在sdf2.1版本中，只能用$setup，$hold和$recovery，$hold。在sdf3.0版本中，增加了$setuphold，$recrem，$removal。分开描述的$setup、$hold、$recovery、$removal不支持negative value。如果要标注负值只能用合起来的$setuphold和$recrem。某工艺的verilog仿真库 $hold(posedge T &&& (shcheckTDlh=== 1'b1), posedge D &&& (shcheckTDlh=== 1'b1),1.0); $hold(posedge T &&& (shcheckTDlh=== 1'b1), negedge D &&& (shcheckTDlh=== 1'b1),1.0); $setup(posedge D &&&(shcheckTDlh === 1'b1), posedge T &&& (shcheckTDlh=== 1'b1),1.0); $setup(negedge D &&&(shcheckTDlh === 1'b1), posedge T &&& (shcheckTDlh=== 1'b1),1.0); $recovery(posedge S,posedge T,1.0); $removal(posedge S,posedge T,1.0);对应3.0版本的SDFTIMINGCHECK (WIDTH (negedge S) (0.103::0.103)) (REMOVAL (posedge S) (posedge T)(0.140::0.140)) (RECOVERY (posedge S) (posedge T)(0.000::0.000)) (WIDTH (negedge T) (0.078::0.078)) (WIDTH (posedge T) (0.094::0.094)) (SETUP (posedge D) (COND shcheckTDlh===1'b1(posedge T)) (0.000::0.000)) (SETUP (negedge D) (COND shcheckTDlh===1'b1(posedge T)) (0.016::0.028)) (HOLD (posedge D) (COND shcheckTDlh===1'b1 (posedgeT)) (0.043::0.049)) (HOLD (negedge D) (COND shcheckTDlh===1'b1 (posedgeT)) (0.009::0.010)) )另一个工艺的verilog仿真库 $setuphold (posedge CP, posedge D, 0, 0,notifier,,, delayed_CP, delayed_D); $setuphold (posedge CP, negedge D, 0, 0,notifier,,, delayed_CP, delayed_D); $recovery (posedge SDN, posedge CP, 0,notifier); $hold (posedge CP, posedge SDN, 0,notifier);对应的2.1版本的SDF： (TIMINGCHECK (WIDTH (negedge SDN) (1.404::1.404)) (HOLD (posedge SDN) (posedge CP)(-0.198::-0.198)) (RECOVERY (posedge SDN) (posedge CP)(0.267::0.267)) (WIDTH (negedge CP) (0.425::0.425)) (WIDTH (posedge CP) (0.440::0.440)) (SETUP (posedge D) (posedge CP)(0.057::0.057)) (SETUP (negedge D) (posedge CP)(0.082::0.082)) (HOLD (posedge D) (posedge CP)(-0.048::-0.048)) (HOLD (negedge D) (posedge CP)(-0.013::-0.013)) )对比两个版本的SDF可以看出3.0的SDF用$removal代替了$hold。第一个verilog仿真库，采用了分开的$setup和$hold，$recovery和$removal。第二个库采用了合起来的$setuphold，但$recovery和$hold还是分开的。所以，第一个库不支持负值的标注；第二个库$setup和$hold支持负值，而$recovery和$hold不支持负值。在SDF版本选择上，第一个库只能用3.0，因为库里用到了$removal。第二个库只能用2.1，因为使用了$hold，如果用3.0的话，Incisive后仿时，会报错，说找不到$removal。结论工厂提供的verilog仿真库总是不那么规范。要么修改库（让工厂修改或自己修改），要么根据库产生符合条件的SDF，但也就不能反标注负值了。提示：pt产生SDF时加参数-version 2.1|3.0，用include来灵活控制，可产生不同需求的SDF。具体可查pt的write_sdf命令的参数。下面是一个例子：write_sdf -version 3.0 \-context verilog \ -include {SETUPHOLD RECREM} \ max.sdf 后仿时看反标注的成功率，如果反标成功率太低，要仔细检查。Incisive的反标率如下：SDF statistics: No. of Pathdelays =37802 Annotated = 100.00% -- No. ofTchecks = 25964 Annotated = 99.60% Total Annotated Percentage Path Delays 37802 37802 100.00 $hold 2306 2306 100.00 $width 12632 12632 100.00 $recovery 2306 2306 100.00 $setuphold 8720 8616 98.81然而VCS并没有这样的百分比报告。

在verilog或者systemverilog中通过systemverilog获得环境变量setenv,getenv 在芯片验证的仿真中，有时候需要从文件中加载一些数据，比如激励、初始化数据、code等等，这些文件路径可以用绝对路径，当然为了其他人也可以用，最好用相对路径，这就需要用到环境变量来做路径的前半段。在module中得到或设置系统环境变量需要用到systemverilog的DPI-C，import C函数，然后在module中的块语句中调用C函数。步骤如下：在要获得环境变量的文件中 import setenv和getenv如下所示，把这两个函数import进去，不需要定义对应的C函数import "DPI-C" function int setenv(input string env_name, input string env_value, input int overwrite);import "DPI-C" function string getenv (input string env_name);直接使用getenv, setenv来获得和设置环境变量module mem read( input [8*200-1: O] mem_file )； initial begin $display("mem_file is %Os", mem_file); end endmodule module dut ( input clk, input wire [31:0]addr, output [31:0] rdata, input [31:0] wdata, input wire wr ); string path; initial begin setenv("PRJDIR", "/project/uart", 1); path = getenv( "PRJDIR"); $display("PRJDIR is %Os", path); setenv( "PRJDIR", "/project/sp", 1); path = getenv( "PRJDIR"); $display("PRJDIR is %0s", path); end mem_read u_mem_rd(.mem_file(path)); endmodule————————————————版权声明：本文为CSDN博主「甲六乙」的原创文章，遵循CC 4.0 BY-SA版权协议，转载请附上原文出处链接及本声明。原文链接：https://blog.csdn.net/m0_38037810/article/details/126136552