Synplicity Synplify Premier v8.9 with Identify v2.5 ( Premier 豪华版是目前功能最强大的一个版本，并附带 Identify 模块)
http://www.synplicity.com/products/synplifypremier/
Synplify Premier v8.9 半导体设计及验证软件供应商Synplicity公司近日对其可编程逻辑器件(PLD)综合软件Synplify 8.9进行了改进。Synplify 软件支持Verilog标准以及新器件及新操作系统(OS)。最新版本的Synplify Pro软件提高了若干项QoR(最终结果质量)，以及增效定时引擎及自动寄存器重新定时功能的增强，能够提高设计人员的产出率，并且性能更佳。
业界领先的基于FPGA的ASIC原型验证综合工具，通过提供诸如团队设计、自动re-timing、快速的编译以及额外的特性来优化设计结果。除了具有B.E.S.T.引擎外，Synplify pro又加入了D.S.T.(Direct Synthesis Technology),SCOPE(Synthesis Constraint Optimization Environment),STAMP和多点优化等技术来满足设计者的需求。Synplify pro提供了和布局布线工具之间的native-link接口来完成Push-Button的流程，使用户只需要点击就可以完成所有的综合和布局布线的工作。基于Synplicety公司的B.E.S.T.引擎，Synplify Pro可以轻松综合数百万门的设计而不需要分割。
Synplify Premier & Synplify Premier withDP软件的推出，进一步巩固了Synplicity在FPGA综合领域的地位。Premier不仅继承了Synplify Pro的全部功能，更加入了众多强大的FPGA综合选项，可以轻松应对复杂的高端FPGA设计和单芯片ASIC 原型验证。
物理综合方面，Premier已经为全球范围内几十家客户成功解决了时序逼近的问题。Synplicity创新的Graph-based的物理综合方法可以为 FPGA 布线使用的走线、开关和布局点创建详细的布线资源图形。有了这样的图形，优化和布局就能围绕线延时和实际可用的资源而不仅仅是距离来展开。布局、布线和优化将在一个步骤中同时完成，如此一来，反复的综合过程都能在工具内部自行完成，从而达到真正的时序收敛。
另外，Synplify Premier整合了一些特有的功能，方便用户使用单颗FPGA进行ASIC原型验证设计。这些特有的功能包括：全面兼容ASIC代码；支持Gated Clock的转换；支持Design Ware的转换。同时，因为Premier整合了在线调试工具Identify，极大的方便了用户进行软硬件协同仿真，确保设计一次成功，从而大大缩短了整个软硬件开发和调试的周期，并能提供更快的timing-closure和提升整体时序表现。
Synplify 详细功能描述
◇ 提供优于传统综合技术的快速的全局编译和综合优化，针对算术模块和数据路径的高性能和高面积利用率的优化；
◇ 提供对设计约束的全面控制，智能化人机界面，提高设计效率，结合具体器件结构，提供最佳性能；
◇ 提供自动的RAM例化过程，提供自动时钟控制和同步/异步清零寄存器结构，自动识别FSM和选择编码方式以达到最佳性能，提供针对FSM的快速的调试和观察工具，自动进行流水处理，以提高电路性能；
◇ 在不改变原代码的情况下，提供内部线网到外部测试管脚的能力，在源代码、RTL视图和Log文件之间的交互标识能力；
◇ 集成化、图形化的分析和调试关键路径的环境；
◇ 支持黑盒子的时序以及管脚信息，支持同时实现多个应用，通过设计划分支持Xilinx模块化设计；
◇ 自动对组合逻辑进行寄存器平衡以提高性能，支持智能化的增量综合。
Synplify & Synplify Premier v8.9
Synplicity（Sunnyvale,Calif.）是全球领先的EDA工具的供应商。公司成立于1994年，总部坐落于美国加州，全球拥有超过300名员工，并在30多个国家和地区设立了销售机构与研发中心。 Synplicity的工具涵盖了可编成逻辑器件（FPGAs、PLDs和CPLDs）的综合，验证，调试和物理综合等领域。公司的宗旨是为系统设计和IC硬件设计工程师提供优秀的解决方案，同时通过创新科技，满足客户最佳结果和最优生产力的需求。
Synplicity’s Synplify Premier software is the ultimate FPGA timing closure and debug solution. It builds upon Synplicity’s industry-leading synthesis technology by adding graph-based physical synthesis and real-time simulator-like visibility into operating FPGA devices. The Synplify Premier tool’s graph-based physical synthesis technology addresses timing closure by merging optimization, placement, routing and generates a fully placed and physically optimized design ready for final routing using the FPGA vendor routing tool. The highly accurate correlation between the Synplify Premier product’s timing estimates and final design timing enables more aggressive optimization resulting in improved device performance. In addition, the Synplify Premier product offers FPGA Designers and ASIC Prototypers the most efficient method of in-system verification of FPGAs. The Synplify Premier software dramatically accelerates the debug process and provides a rapid and incremental method for finding elusive design problems.
Graph-Based Physical Synthesis
Invented by Synplicity, graph-based physical synthesis improves timing closure by means of a single-pass physical synthesis flow for 90nm FPGAs. Unlike ASICs, proximity does not imply better timing in FPGAs. In graph-based physical synthesis, pre-existing wires, switches, and placement sites used for routing an FPGA can be represented as a detailed routing resource graph. The notion of distance then changes to a measure of delay and availability of wires. The Synplify Premier solution's graph-based physical synthesis technology merges optimization, placement, and routing to generate a fully placed and physically optimized netlist, providing rapid timing closure and a 5 - 20% timing improvement.
Simulator-Like Visibility Into a Live FPGA
The Synplify Premier solution quickly finds functional errors in FPGA designs by providing simulator-like visibility into operating FPGA hardware. Based upon technology from the Identify® product, the Synplify Premier tool has integrated debugging software that allows designers to annotate signals and conditions they want to monitor directly in their RTL code. Once the FPGA has been programmed, the RTL debugger is run, allowing users to view actual signal values from a running FPGA directly in their RTL code and debug it, in-system, and at the target operating speed. Advanced triggering helps pinpoint design problems
With the addition of graph-based physical and source-level, in-circuit debugging to the world's best FPGA synthesis technology, the Synplify Premier product is the industry's most comprehensive and productive FPGA design solution.
ASIC Verification
For FPGA users that are prototyping an ASIC, Synplify Premier accepts inputs that are compatible with industry-leading ASIC synthesis tools, allowing you to quickly retarget your FPGA prototype design to an ASIC. Compatibility features includes support for basic Designware components, automatic gated clock conversion, and the use of SDC constraints.
SDC and DesignWare are both trademarks of Synopsys, Inc.
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